Unit convenor and teaching staff |
Unit convenor and teaching staff
Head Tutor
Niras Cheeckottu Vayalil
lecturer
Yinan Kong
tutor
Naila Mukhtar
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Credit points |
Credit points
3
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Prerequisites |
Prerequisites
(39cp at 100 level or above) including ELEC241
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Corequisites |
Corequisites
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Co-badged status |
Co-badged status
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Unit description |
Unit description
This unit is a sequence of lectures and practical work on digital systems designs, including: behavioural specification and description; architecture and structure design; software/hardware co-design; technology mapping, verification and test. For greater complexity we choose Field-Programmable Gate Arrays (FPGAs) and a variety of software provided by the manufacturer (Xilinx), including Boolean equations, schematic entry, state machines, and a high-level design language (VHDL), itself supporting a variety of modes. This unit gives students the skills and knowledge needed to design modern digital systems.
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Information about important academic dates including deadlines for withdrawing from units are available at https://www.mq.edu.au/study/calendar-of-dates
On successful completion of this unit, you will be able to:
Student Responsibilities
Be familiar with University policy and College procedures and act in accordance with those policy and procedures.
It is the responsibility of the student to retain a copy of any work submitted. Students must produce these documents upon request. Copies should be retained until the end of the grade appeal period each term.
Student is to perform the required due diligent for their assessment grade and rectify as soon as possible upon finding any errors.
Notifications
Formal notification of assessment tasks, grading rubrics and due dates will be posted on iLearn. Although all reasonable measures to ensure the information is accurate, The University reserves the right to make changes without notice. Each student is responsible for checking iLearn for changes and updates.
Practical sessions
There are twelve practical sessions (each of three hours duration) starting in Week 2. Students will work individually in the first four sessions and work in teams of two in the other eight. Students will attend one practical session each week. On the completion of each session, each individual or group must complete and submit a “check-list” that itemizes each section of the practical. Each item is to be initialed by the group members on completion of the work. Individual contribution and performance are assessed in group practicals. Your performance as recorded in your copies of the practical notes and summarized by your check-list will be used in the assessment of your practical work.
Food and drink are not permitted in the laboratory. Students will not be permitted to enter the laboratory without appropriate footwear. Thongs and sandals are not acceptable.
Report and Assignment Tasks
Each team of two students will be required to submit two reports. One is based on the first four practicals and the other is based on the two team projects. Reports should be submitted by the next Monday following the completion of the practical session of the report.
Assignment submissions and plagiarism policies
All assignments and reports must be submitted electronically through iLearn (in pdf format). Submissions will undergo plagiarism checkers using the turnitin software and any work deemed to have 30% or higher similarity score may incur academic penalty. For more details on the policies of academic penalties relating to academic honesty, please refer to the policies and procedures section below.
Submissions are expected to be typed set in a logical layout and sequence. Markers WILL NOT grade poorly organized or illegible scans or drafts. The expected workload includes preparation of final copies and clear diagrams.
Late submissions or absences from tutorials and laboratories will not be accepted without prior arrangement made at least one week before the submission date. Extenuating circumstances will be considered upon lodgement of a formal notice of disruption of studies.
Hurdle Requirement
The final examination is a hurdle requirement because it is the only reliable assessment of individual performance for this unit. A passing grade of 50% or more in the final examination is a condition of passing this unit. Students who make a serious attempt but fail to meet the hurdle requirement will be given one further opportunity to pass. A serious attempt is defined as achievement of a mark of 40% or greater.
Grading and passing requirement for unit
For further details about grading, please refer below in the policies and procedures section.
In order to pass this unit a student must obtain a mark of 50 or more for the unit (i.e. obtain a passing grade P/ CR/ D/ HD).
Final Examinations
Final examinations will typically take place at the end of the semester. For further information, please refer to the Examination Timetable website on www.mq.edu.au
Supplementary Examination
Applications for a supplementary examination (based on medical reasons or misadventure) will only be considered if students have gained passes in the practicals and reports.
Name | Weighting | Hurdle | Due |
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Practical 1 | 2% | No | Week 2 |
Practical 2 | 2% | No | Week 3 |
Practical 3 | 3% | No | Week 4 |
Practical 4 | 3% | No | Week 5 |
Report 1 | 3% | No | Week 6 |
Practical 5 | 2% | No | Week 6 |
Practical 6 | 2% | No | Week 7 |
Practical 7 | 2% | No | Week 8 |
Practical 8 | 2% | No | Week 9 |
Project 1 Deliverables | 4% | No | Week 9 |
Practical 9 | 2% | No | Week 10 |
Practical 10 | 2% | No | Week 11 |
Practical 11 | 2% | No | Week 12 |
Practical 12 | 2% | No | Week 13 |
Project 2 Deliverables | 4% | No | Week 13 |
Report 2 | 3% | No | Week 14 |
Exam | 60% | Yes | Exam Period |
Due: Week 2
Weighting: 2%
Schematic Capture and Hierarchical Design
Due: Week 3
Weighting: 2%
Getting Started with VHDL and Modelsim
Due: Week 4
Weighting: 3%
Basic VHDL Design Examples
Due: Week 5
Weighting: 3%
Basic VHDL Design Examples
Due: Week 6
Weighting: 3%
Report on Practical 1 to 4
Due: Week 6
Weighting: 2%
Team Project – Computer Design
Due: Week 7
Weighting: 2%
Team Project – Computer Design
Due: Week 8
Weighting: 2%
Team Project – Computer Design
Due: Week 9
Weighting: 2%
Team Project – Computer Design
Due: Week 9
Weighting: 4%
Project 1 Deliverables
Due: Week 10
Weighting: 2%
Team Project – Traffic Light Controller Design and Implementation
Due: Week 11
Weighting: 2%
Team Project – Traffic Light Controller Design and Implementation
Due: Week 12
Weighting: 2%
Team Project – Traffic Light Controller Design and Implementation
Due: Week 13
Weighting: 2%
Team Project – Traffic Light Controller Design and Implementation
Due: Week 13
Weighting: 4%
Project 2 Deliverables
Due: Week 14
Weighting: 3%
Report 2 on Project 1 and 2
Due: Exam Period
Weighting: 60%
This is a hurdle assessment task (see assessment policy for more information on hurdle assessment tasks)
Exam (one 3-hour closed-book exam)
Lectures |
There are two lectures per week. Lecture topics are provided in the (attached) timetable. From time to time, important announcements and notices will be made in the lectures. It is the responsibility of the student to be aware of these announcements and notices. |
Technology used and required |
Technology used: Xilinx FPGAs, Xilinx ISE & XST and VHDL Technology required: microcontrollers, programmable logic devices, e.g. GAL, PAL, etc. |
Extension requests |
Must be supported by evidence of medical conditions or misadventure. |
Text book |
Charles, R. H. and John, L. K., “Digital Systems Design Using VHDL”, Second edition, Thompson, 2008 |
Reference book(s) |
Vahid, F. and Lysecky, R., VHDL For Digital Design, Wiley 2007 Weste, N. and Harris, D., “CMOS VLSI Design -- A Circuit and Systems Perspecitive”, 3rd ed., (Addison-Wesley 2004) Andrew Rushton, “VHDL for Logic Synthesis (Second Edition)”, John Wiley and Sons, 2001 |
Notes |
Notes for the practical sessions are available online. Each student is required to preview the corresponding notes before each practical session. |
Macquarie University policies and procedures are accessible from Policy Central. Students should be aware of the following policies in particular with regard to Learning and Teaching:
Academic Honesty Policy http://mq.edu.au/policy/docs/academic_honesty/policy.html
Assessment Policy http://mq.edu.au/policy/docs/assessment/policy_2016.html
Grade Appeal Policy http://mq.edu.au/policy/docs/gradeappeal/policy.html
Complaint Management Procedure for Students and Members of the Public http://www.mq.edu.au/policy/docs/complaint_management/procedure.html
Disruption to Studies Policy (in effect until Dec 4th, 2017): http://www.mq.edu.au/policy/docs/disruption_studies/policy.html
Special Consideration Policy (in effect from Dec 4th, 2017): https://staff.mq.edu.au/work/strategy-planning-and-governance/university-policies-and-procedures/policies/special-consideration
In addition, a number of other policies can be found in the Learning and Teaching Category of Policy Central.
Macquarie University students have a responsibility to be familiar with the Student Code of Conduct: https://students.mq.edu.au/support/student_conduct/
Results shown in iLearn, or released directly by your Unit Convenor, are not confirmed as they are subject to final approval by the University. Once approved, final results will be sent to your student email address and will be made available in eStudent. For more information visit ask.mq.edu.au.
Macquarie University provides a range of support services for students. For details, visit http://students.mq.edu.au/support/
Learning Skills (mq.edu.au/learningskills) provides academic writing resources and study strategies to improve your marks and take control of your study.
Students with a disability are encouraged to contact the Disability Service who can provide appropriate help with any issues that arise during their studies.
For all student enquiries, visit Student Connect at ask.mq.edu.au
For help with University computer systems and technology, visit http://www.mq.edu.au/about_us/offices_and_units/information_technology/help/.
When using the University's IT, you must adhere to the Acceptable Use of IT Resources Policy. The policy applies to all who connect to the MQ network including students.
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