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ELEC643 – Digital Systems Design

2017 – S2 Day

General Information

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Unit convenor and teaching staff Unit convenor and teaching staff Head Tutor
Niras
lecturer
Yinan Kong
Credit points Credit points
4
Prerequisites Prerequisites
Admission to MEng
Corequisites Corequisites
Co-badged status Co-badged status
Unit description Unit description
This unit is a sequence of lectures and practical work on digital systems designs, including: behavioural specification and description; architecture and structure design; software/hardware co-design; technology mapping, verification and test. For greater complexity we choose Field-Programmable Gate Arrays (FPGAs) and a variety of software provided by the manufacturer (Xilinx), including Boolean equations, schematic entry, state machines, and a high-level design language (VHDL), itself supporting a variety of modes. This unit gives students the skills and knowledge needed to design modern digital systems.

Important Academic Dates

Information about important academic dates including deadlines for withdrawing from units are available at http://students.mq.edu.au/student_admin/enrolmentguide/academicdates/

Learning Outcomes

  1. Conceptual understanding of the FPGA and VHDL concepts which underpin the subject.
  2. Ability to apply VHDL programming to the implementation of electronic circuits on FPGAs.
  3. Ability to conduct complex digital systems design within an integrated engineering team.
  4. In depth understanding of the characteristics of CMOS technology, the process of CMOS fabrication and the architecture of a microcontroller.
  5. In depth understanding of digital systems design with industry based Hardware Description Language.

General Assessment Information

 

Student Responsibilities

Be familiar with University policy and College procedures and act in accordance with those policy and procedures.

It is the responsibility of the student to retain a copy of any work submitted. Students must produce these documents upon request. Copies should be retained until the end of the grade appeal period each term.

Student is to perform the required due diligent for their assessment grade and rectify as soon as possible upon finding any errors.

 

Notifications

Formal notification of assessment tasks, grading rubrics and due dates will be posted on iLearn. Although all reasonable measures to ensure the information is accurate, The University reserves the right to make changes without notice. Each student is responsible for checking iLearn for changes and updates.

 

Practical sessions

There are twelve practical sessions (each of three hours duration) starting in Week 2. Students will work individually in the first four sessions and work in teams of two in the other eight. Students will attend one practical session each week. On the completion of each session, each individual or group must complete and submit a “check-list” that itemizes each section of the practical. Each item is to be initialed by the group members on completion of the work. Individual contribution and performance are assessed in group practicals.  Your performance as recorded in your copies of the practical notes and summarized by your check-list will be used in the assessment of your practical work.

Food and drink are not permitted in the laboratory. Students will not be permitted to enter the laboratory without appropriate footwear. Thongs and sandals are not acceptable

 

Report and Assignment Tasks

Each team of two students will be required to submit two reports. One is based on the first four practicals and the other is based on the two team projects. Reports should be submitted by the next Monday following the completion of the practical session of the report.

 

Assignment submissions and plagiarism policies

All assignments and reports must be submitted electronically through iLearn (in pdf format). Submissions will undergo plagiarism checkers using the turnitin software and any work deemed to have 30% or higher similarity score may incur academic penalty. For more details on the policies of academic penalties relating to academic honesty, please refer to the policies and procedures section below.

Submissions are expected to be typed set in a logical layout and sequence. Markers WILL NOT grade poorly organized or illegible scans or drafts. The expected workload includes preparation of final copies and clear diagrams.

Late submissions or absences from tutorials and laboratories will not be accepted without prior arrangement made at least one week before the submission date. Extenuating circumstances will be considered upon lodgement of a formal notice of disruption of studies.

 

Hurdle Requirement

The final examination is a hurdle requirement because it is the only reliable assessment of individual performance for this unit. A passing grade of 50% or more in the final examination is a condition of passing this unit. Students who make a serious attempt but fail to meet the hurdle requirement will be given one further opportunity to pass. A serious attempt is defined as achievement of a mark of 40% or greater.

 

Grading and passing requirement for unit

For further details about grading, please refer below in the policies and procedures section.

In order to pass this unit a student must obtain a mark of 50 or more for the unit (i.e. obtain a passing grade P/ CR/ D/ HD).

 

Final Examinations

Final examinations will typically take place at the end of the semester. For further information, please refer to the Examination Timetable website on www.mq.edu.au

 

Supplementary Examination

Applications for a supplementary examination (based on medical reasons or misadventure) will only be considered if students have gained passes in the practicals and reports.

 

Assessment Tasks

Name Weighting Due
Practical 1 2% Week 2
Practical 2 2% Week 3
Practical 3 3% Week 4
Practical 4 3% Week 5
Report 1 3% Week 6
Practical 5 2% Week 6
Practical 6 2% Week 7
Practical 7 2% Week 8
Practical 8 2% Week 9
Project 1 Deliverables 4% Week 9
Practical 9 2% Week 10
Practical 10 2% Week 11
Practical 11 2% Week 12
Practical 12 2% Week 13
Project 2 Deliverables 4% Week 13
Report 2 3% Week 14
Exam 60% Exam Period

Practical 1

Due: Week 2
Weighting: 2%

Schematic Capture and Hierarchical Design


This Assessment Task relates to the following Learning Outcomes:
  • Conceptual understanding of the FPGA and VHDL concepts which underpin the subject.

Practical 2

Due: Week 3
Weighting: 2%

Getting Started with VHDL and Modelsim


This Assessment Task relates to the following Learning Outcomes:
  • Conceptual understanding of the FPGA and VHDL concepts which underpin the subject.

Practical 3

Due: Week 4
Weighting: 3%

Basic VHDL Design Examples


This Assessment Task relates to the following Learning Outcomes:
  • Conceptual understanding of the FPGA and VHDL concepts which underpin the subject.

Practical 4

Due: Week 5
Weighting: 3%

Basic VHDL Design Examples


This Assessment Task relates to the following Learning Outcomes:
  • Conceptual understanding of the FPGA and VHDL concepts which underpin the subject.

Report 1

Due: Week 6
Weighting: 3%

Report on Practical 1 to 4


This Assessment Task relates to the following Learning Outcomes:
  • Conceptual understanding of the FPGA and VHDL concepts which underpin the subject.

Practical 5

Due: Week 6
Weighting: 2%

Team Project – Computer Design


This Assessment Task relates to the following Learning Outcomes:
  • Ability to apply VHDL programming to the implementation of electronic circuits on FPGAs.
  • In depth understanding of the characteristics of CMOS technology, the process of CMOS fabrication and the architecture of a microcontroller.

Practical 6

Due: Week 7
Weighting: 2%

Team Project – Computer Design


This Assessment Task relates to the following Learning Outcomes:
  • Ability to apply VHDL programming to the implementation of electronic circuits on FPGAs.
  • In depth understanding of the characteristics of CMOS technology, the process of CMOS fabrication and the architecture of a microcontroller.

Practical 7

Due: Week 8
Weighting: 2%

Team Project – Computer Design


This Assessment Task relates to the following Learning Outcomes:
  • Ability to apply VHDL programming to the implementation of electronic circuits on FPGAs.

Practical 8

Due: Week 9
Weighting: 2%

Team Project – Computer Design


This Assessment Task relates to the following Learning Outcomes:
  • Ability to apply VHDL programming to the implementation of electronic circuits on FPGAs.
  • In depth understanding of the characteristics of CMOS technology, the process of CMOS fabrication and the architecture of a microcontroller.
  • In depth understanding of digital systems design with industry based Hardware Description Language.

Project 1 Deliverables

Due: Week 9
Weighting: 4%

Project 1 Deliverables


This Assessment Task relates to the following Learning Outcomes:
  • Ability to apply VHDL programming to the implementation of electronic circuits on FPGAs.
  • In depth understanding of the characteristics of CMOS technology, the process of CMOS fabrication and the architecture of a microcontroller.
  • In depth understanding of digital systems design with industry based Hardware Description Language.

Practical 9

Due: Week 10
Weighting: 2%

Team Project – Traffic Light Controller Design and Implementation


This Assessment Task relates to the following Learning Outcomes:
  • Ability to conduct complex digital systems design within an integrated engineering team.

Practical 10

Due: Week 11
Weighting: 2%

Team Project – Traffic Light Controller Design and Implementation


This Assessment Task relates to the following Learning Outcomes:
  • Ability to conduct complex digital systems design within an integrated engineering team.

Practical 11

Due: Week 12
Weighting: 2%

Team Project – Traffic Light Controller Design and Implementation


This Assessment Task relates to the following Learning Outcomes:
  • Ability to conduct complex digital systems design within an integrated engineering team.

Practical 12

Due: Week 13
Weighting: 2%

Team Project – Traffic Light Controller Design and Implementation


This Assessment Task relates to the following Learning Outcomes:
  • Ability to conduct complex digital systems design within an integrated engineering team.

Project 2 Deliverables

Due: Week 13
Weighting: 4%

Project 2 Deliverables


This Assessment Task relates to the following Learning Outcomes:
  • Ability to conduct complex digital systems design within an integrated engineering team.

Report 2

Due: Week 14
Weighting: 3%

Report 2 on Project 1 and 2


This Assessment Task relates to the following Learning Outcomes:
  • Ability to apply VHDL programming to the implementation of electronic circuits on FPGAs.
  • Ability to conduct complex digital systems design within an integrated engineering team.
  • In depth understanding of the characteristics of CMOS technology, the process of CMOS fabrication and the architecture of a microcontroller.
  • In depth understanding of digital systems design with industry based Hardware Description Language.

Exam

Due: Exam Period
Weighting: 60%

Exam (one 3-hour closed-book exam)


This Assessment Task relates to the following Learning Outcomes:
  • Conceptual understanding of the FPGA and VHDL concepts which underpin the subject.
  • Ability to apply VHDL programming to the implementation of electronic circuits on FPGAs.
  • In depth understanding of the characteristics of CMOS technology, the process of CMOS fabrication and the architecture of a microcontroller.

Delivery and Resources

Lectures

There are two lectures per week.  Lecture topics are provided in the (attached) timetable. From time to time, important announcements and notices will be made in the lectures. It is the responsibility of the student to be aware of these announcements and notices.

Technology used and required

Technology used: Xilinx FPGAs, Xilinx ISE & XST and VHDL

Technology required: microcontrollers, programmable logic devices, e.g. GAL, PAL, etc. 

Extension requests

Must be supported by evidence of medical conditions or misadventure.

Text book

Charles, R. H. and John, L. K., “Digital Systems Design Using VHDL”, Second edition, Thompson, 2008

Reference book(s)

Vahid, F. and Lysecky, R., VHDL For Digital Design, Wiley 2007

Weste, N. and Harris, D., “CMOS VLSI Design -- A Circuit and Systems Perspecitive”, 3rd ed., (Addison-Wesley 2004)

Andrew Rushton, “VHDL for Logic Synthesis (Second Edition)”, John Wiley and Sons, 2001

Notes

Notes for the practical sessions are available online. Each student is required to preview the corresponding notes before each practical session.

Policies and Procedures

Macquarie University policies and procedures are accessible from Policy Central. Students should be aware of the following policies in particular with regard to Learning and Teaching:

Academic Honesty Policy http://mq.edu.au/policy/docs/academic_honesty/policy.html

Assessment Policy http://mq.edu.au/policy/docs/assessment/policy_2016.html

Grade Appeal Policy http://mq.edu.au/policy/docs/gradeappeal/policy.html

Complaint Management Procedure for Students and Members of the Public http://www.mq.edu.au/policy/docs/complaint_management/procedure.html​

Disruption to Studies Policy http://www.mq.edu.au/policy/docs/disruption_studies/policy.html The Disruption to Studies Policy is effective from March 3 2014 and replaces the Special Consideration Policy.

In addition, a number of other policies can be found in the Learning and Teaching Category of Policy Central.

Student Code of Conduct

Macquarie University students have a responsibility to be familiar with the Student Code of Conduct: https://students.mq.edu.au/support/student_conduct/

Results

Results shown in iLearn, or released directly by your Unit Convenor, are not confirmed as they are subject to final approval by the University. Once approved, final results will be sent to your student email address and will be made available in eStudent. For more information visit ask.mq.edu.au.

Student Support

Macquarie University provides a range of support services for students. For details, visit http://students.mq.edu.au/support/

Learning Skills

Learning Skills (mq.edu.au/learningskills) provides academic writing resources and study strategies to improve your marks and take control of your study.

Student Enquiry Service

For all student enquiries, visit Student Connect at ask.mq.edu.au

Equity Support

Students with a disability are encouraged to contact the Disability Service who can provide appropriate help with any issues that arise during their studies.

IT Help

For help with University computer systems and technology, visit http://www.mq.edu.au/about_us/offices_and_units/information_technology/help/

When using the University's IT, you must adhere to the Acceptable Use of IT Resources Policy. The policy applies to all who connect to the MQ network including students.

Graduate Capabilities

Discipline Specific Knowledge and Skills

Our graduates will take with them the intellectual development, depth and breadth of knowledge, scholarly understanding, and specific subject content in their chosen fields to make them competent and confident in their subject or profession. They will be able to demonstrate, where relevant, professional technical competence and meet professional standards. They will be able to articulate the structure of knowledge of their discipline, be able to adapt discipline-specific knowledge to novel situations, and be able to contribute from their discipline to inter-disciplinary solutions to problems.

This graduate capability is supported by:

Learning outcomes

  • Conceptual understanding of the FPGA and VHDL concepts which underpin the subject.
  • In depth understanding of the characteristics of CMOS technology, the process of CMOS fabrication and the architecture of a microcontroller.

Assessment tasks

  • Practical 1
  • Practical 2
  • Practical 3
  • Practical 4
  • Report 1
  • Practical 5
  • Practical 6
  • Practical 8
  • Project 1 Deliverables
  • Report 2
  • Exam

Problem Solving and Research Capability

Our graduates should be capable of researching; of analysing, and interpreting and assessing data and information in various forms; of drawing connections across fields of knowledge; and they should be able to relate their knowledge to complex situations at work or in the world, in order to diagnose and solve problems. We want them to have the confidence to take the initiative in doing so, within an awareness of their own limitations.

This graduate capability is supported by:

Learning outcomes

  • Conceptual understanding of the FPGA and VHDL concepts which underpin the subject.
  • In depth understanding of the characteristics of CMOS technology, the process of CMOS fabrication and the architecture of a microcontroller.

Assessment tasks

  • Practical 1
  • Practical 2
  • Practical 3
  • Practical 4
  • Report 1
  • Practical 5
  • Practical 6
  • Practical 8
  • Project 1 Deliverables
  • Report 2
  • Exam

Effective Communication

We want to develop in our students the ability to communicate and convey their views in forms effective with different audiences. We want our graduates to take with them the capability to read, listen, question, gather and evaluate information resources in a variety of formats, assess, write clearly, speak effectively, and to use visual communication and communication technologies as appropriate.

This graduate capability is supported by:

Learning outcomes

  • Ability to apply VHDL programming to the implementation of electronic circuits on FPGAs.
  • Ability to conduct complex digital systems design within an integrated engineering team.
  • In depth understanding of the characteristics of CMOS technology, the process of CMOS fabrication and the architecture of a microcontroller.

Assessment tasks

  • Practical 5
  • Practical 6
  • Practical 8
  • Project 1 Deliverables
  • Practical 9
  • Practical 10
  • Practical 11
  • Practical 12
  • Project 2 Deliverables
  • Report 2
  • Exam

Capable of Professional and Personal Judgement and Initiative

We want our graduates to have emotional intelligence and sound interpersonal skills and to demonstrate discernment and common sense in their professional and personal judgement. They will exercise initiative as needed. They will be capable of risk assessment, and be able to handle ambiguity and complexity, enabling them to be adaptable in diverse and changing environments.

This graduate capability is supported by:

Learning outcome

  • Ability to conduct complex digital systems design within an integrated engineering team.

Assessment tasks

  • Practical 9
  • Practical 10
  • Practical 11
  • Practical 12
  • Project 2 Deliverables
  • Report 2

Critical, Analytical and Integrative Thinking

We want our graduates to be capable of reasoning, questioning and analysing, and to integrate and synthesise learning and knowledge from a range of sources and environments; to be able to critique constraints, assumptions and limitations; to be able to think independently and systemically in relation to scholarly activity, in the workplace, and in the world. We want them to have a level of scientific and information technology literacy.

This graduate capability is supported by:

Learning outcomes

  • Conceptual understanding of the FPGA and VHDL concepts which underpin the subject.
  • In depth understanding of the characteristics of CMOS technology, the process of CMOS fabrication and the architecture of a microcontroller.

Assessment tasks

  • Practical 1
  • Practical 2
  • Practical 3
  • Practical 4
  • Report 1
  • Practical 5
  • Practical 6
  • Practical 8
  • Project 1 Deliverables
  • Report 2
  • Exam

Creative and Innovative

Our graduates will also be capable of creative thinking and of creating knowledge. They will be imaginative and open to experience and capable of innovation at work and in the community. We want them to be engaged in applying their critical, creative thinking.

This graduate capability is supported by:

Learning outcomes

  • Ability to apply VHDL programming to the implementation of electronic circuits on FPGAs.
  • Ability to conduct complex digital systems design within an integrated engineering team.
  • In depth understanding of the characteristics of CMOS technology, the process of CMOS fabrication and the architecture of a microcontroller.

Assessment tasks

  • Practical 5
  • Practical 6
  • Practical 8
  • Project 1 Deliverables
  • Practical 9
  • Practical 10
  • Practical 11
  • Practical 12
  • Project 2 Deliverables
  • Report 2
  • Exam

Engaged and Ethical Local and Global citizens

As local citizens our graduates will be aware of indigenous perspectives and of the nation's historical context. They will be engaged with the challenges of contemporary society and with knowledge and ideas. We want our graduates to have respect for diversity, to be open-minded, sensitive to others and inclusive, and to be open to other cultures and perspectives: they should have a level of cultural literacy. Our graduates should be aware of disadvantage and social justice, and be willing to participate to help create a wiser and better society.

This graduate capability is supported by:

Learning outcomes

  • Ability to apply VHDL programming to the implementation of electronic circuits on FPGAs.
  • Ability to conduct complex digital systems design within an integrated engineering team.
  • In depth understanding of the characteristics of CMOS technology, the process of CMOS fabrication and the architecture of a microcontroller.

Assessment tasks

  • Practical 5
  • Practical 6
  • Practical 8
  • Project 1 Deliverables
  • Practical 9
  • Practical 10
  • Practical 11
  • Practical 12
  • Project 2 Deliverables
  • Report 2
  • Exam

Socially and Environmentally Active and Responsible

We want our graduates to be aware of and have respect for self and others; to be able to work with others as a leader and a team player; to have a sense of connectedness with others and country; and to have a sense of mutual obligation. Our graduates should be informed and active participants in moving society towards sustainability.

This graduate capability is supported by:

Learning outcome

  • Ability to conduct complex digital systems design within an integrated engineering team.

Assessment tasks

  • Practical 9
  • Practical 10
  • Practical 11
  • Practical 12
  • Project 2 Deliverables
  • Report 2

Commitment to Continuous Learning

Our graduates will have enquiring minds and a literate curiosity which will lead them to pursue knowledge for its own sake. They will continue to pursue learning in their careers and as they participate in the world. They will be capable of reflecting on their experiences and relationships with others and the environment, learning from them, and growing - personally, professionally and socially.

This graduate capability is supported by:

Learning outcomes

  • Ability to conduct complex digital systems design within an integrated engineering team.
  • In depth understanding of the characteristics of CMOS technology, the process of CMOS fabrication and the architecture of a microcontroller.

Assessment tasks

  • Practical 5
  • Practical 6
  • Practical 8
  • Project 1 Deliverables
  • Practical 9
  • Practical 10
  • Practical 11
  • Practical 12
  • Project 2 Deliverables
  • Report 2
  • Exam

Changes in response to student feedback

Lecturer in charge and tutors have weekly fixed time slots to provide response to student feedback.