Grading and passing requirement for unit

In order to pass this unit a student must obtain a mark of 50 or more for the unit (i.e. obtain a passing grade P/ CR/ D/ HD).

For further details about grading, please refer below in the policies and procedures section.

Hurdle Requirements

There are three hurdle requirements for passing this unit. Participation in practical sessions is a hurdle requirement. Students are required to participate in at least 75% of practical sessions to pass this unit. You must score 50% or more in Quiz 2 to pass the hurdle. You will be offered a second attempt at Quiz 2 if you fail to meet the minimum required mark to pass the hurdle. You must score 50% or more for the Complex Design Task to pass the hurdle. 

Late Assessment Submission Penalty 

From 1 July 2022, Students enrolled in Session based units with written assessments will have the following university standard late penalty applied. Please see https://students.mq.edu.au/study/assessment-exams/assessments for more information.    Unless a Special Consideration request has been submitted and approved, a 5% penalty (of the total possible mark) will be applied each day a written assessment is not submitted, up until the 7th day (including weekends). After the 7th day, a grade of '0' will be awarded even if the assessment is submitted. Submission time for all written assessments is set at 11:55 pm. A 1-hour grace period is provided to students who experience a technical concern.    For any late submission of time-sensitive tasks, such as scheduled tests/exams, performance assessments/presentations, and/or scheduled practical assessments/labs, students need to submit an application for Special Consideration.  

Assessments where Late Submissions will be accepted 

In this unit, late submissions will accepted as follows: 

• Student Engagement - NO, unless Special Consideration is Granted 
• Quiz 1, 2, 3 - NO, unless Special Consideration is Granted 
• Minor Project - YES, Standard Late Penalty applies
• Complex Design Task - YES, Standard Late Penalty applies

Each week students are expected to attend a 2-hour lectorial and a 3-hour practical session on campus. There is pre-work that needs to be completed before each practical session, which may include watching videos and completing exercises. 

This is a hands-on unit, centred around physical circuits. We will be using physical trainer boards to build digital circuits and experiment with those circuits, along with buidling full digital systems on an FPGA. All students are expected to attend their practical session on campus to access the hardware. To describe digital circuits and systems, we will be using Xilinx Vivado Design tools which allows simulation and synthesis of designs. The software is available on the computers in the lab, but students are also expected to install it onto their own computers so that they can do the pre-work. You will need a Windows laptop with a minimum of 8 GB RAM and ~40 GB hard drive space.

The text book for this unit is Introduction to Logic Circuits & Logic Design with Verilog, 2nd Edition by Brock J. LaMeres. It is available free of charge to students through the library. 

Topics covered in this unit include: analog-to-digital conversion, Boolean algebra, logic gates, digital circuit design techniques, combinational logic, state machines, hardware description languages, and field programmable gate arrays. 

In response to student feedback, the final exam has been replaced with 3 quizzes throughout the semester to provide more timely feedback on learning progress. The complex design task is now a hurdle for passing the unit.