Unit Guide

General Information

Unit convenor and teaching staff	Unit convenor and teaching staff Unit Convener and Lecturer in Charge Ediz Cetin ediz.cetin@mq.edu.au Contact via Contact via Email 44 Waterloo Road, Room: 117 Monday’s 14:00 – 16:00 hrs.
Credit points	Credit points 10
Prerequisites	Prerequisites Admission to MEngElecEng and 30cp at 3000 level or above
Corequisites	Corequisites
Co-badged status	Co-badged status
Unit description	Unit description This unit looks at VLSI technology from the perspective of an enabling platform for digital, analog, and complete system solutions. By taking a systems approach driven by the applications and algorithms, the VLSI design is driven toward a more optimised solution by analysis at higher levels.

Important Academic Dates

Information about important academic dates including deadlines for withdrawing from units are available at https://www.mq.edu.au/study/calendar-of-dates

Learning Outcomes

On successful completion of this unit, you will be able to:

ULO1: Demonstrate an understanding of foundational impact of implementation technology and develop advanced VLSI engineering skills.
ULO2: Evaluate systems and algorithms in regard to their implementation as VLSI integrated circuits.
ULO3: Incorporate design trade-offs involving area, power and performance as a result of algorithm and architecture selection for practical problems requiring VLSI solutions.
ULO4: Demonstrate competency in the practical use of standard VLSI work products for communication and documentation of engineering processes.
ULO5: Execute a project to implement an application or VLSI algorithm and produce requirements, specifications, and designs for low-power, area and/or high performance.

General Assessment Information

Grading and passing requirement for unit

In order to pass this unit a student must obtain a mark of 50 or more for the unit (i.e. obtain a passing grade P/CR/D/HD).

For further details about grading, please refer below in the policies and procedures section.

Hurdle Requirements

There are no hurdle requirements.

Late Assessment Submission Penalty

From 1 July 2022, Students enrolled in Session based units with written assessments will have the following university standard late penalty applied. Please see https://students.mq.edu.au/study/assessment-exams/assessments for more information.

Unless a Special Consideration request has been submitted and approved, a 5% penalty (of the total possible mark) will be applied each day a written assessment is not submitted, up until the 7^th day (including weekends). After the 7^th day, a grade of '0' will be awarded even if the assessment is submitted. Submission time for all written assessments is set at 11:55 pm. A 1-hour grace period is provided to students who experience a technical concern.

For any late submission of time-sensitive tasks, such as scheduled tests/exams, performance assessments/presentations, and/or scheduled practical assessments/labs, students need to submit an application for Special Consideration.

Assessments where Late Submissions will be accepted

In this unit, late submissions will accepted as follows:

Assignment 1 report, Assignment 2 report and Project Report – YES, Standard Late Penalty applies

Assessment Tasks

Name	Weighting	Hurdle	Due
Assignment 1	10%	No	Week 4
Assignment 1 Defence	15%	No	Week 4
Assignment 2	10%	No	Week 7
Assignment 2 Defence	15%	No	Week 7
Project Report	20%	No	Week 13
Project Defence	30%	No	Exam Period