Unit Guide

General Information

Unit convenor and teaching staff	Unit convenor and teaching staff Unit Convener and Lecturer in Charge Ediz Cetin ediz.cetin@mq.edu.au Contact via Contact via Email 44 Waterloo Road, Room: 117 Monday’s 14:00 – 16:00 hrs. Tutor Richard Vu richard.vu@mq.edu.au Contact via Contact via Email 44 Waterloo Road
Credit points	Credit points 10
Prerequisites	Prerequisites Admission to MEngElecEng
Corequisites	Corequisites
Co-badged status	Co-badged status
Unit description	Unit description This unit will provide an in-depth introduction to the principal concepts, foundations, and methodologies for the design of trustworthy security systems on hardware. Specifically, the unit aims to equip students with the skills needed to build secure and trustworthy hardware using Field Programmable Gate Array (FPGA) technology. The unit will cover topics in cryptosystems, error coding techniques as well as state-of-the-art hardware security systems. The unit will also provide the students with an understanding of and fluency in the quantitative evaluation of design alternatives while considering design metrics such as performance, power dissipation, cost and security.

Important Academic Dates

Information about important academic dates including deadlines for withdrawing from units are available at https://www.mq.edu.au/study/calendar-of-dates

Learning Outcomes

On successful completion of this unit, you will be able to:

ULO1: Demonstrate a detailed understanding of computer system architectures and the ways in which systems are vulnerable to attack from untrusted entities.
ULO2: Demonstrate a detailed understanding of chip-level, PCB-level and System-level attacks and the countermeasures employed to mitigate security risks.
ULO3: Describe, with advanced expertise, the relationship between the security level of a hardware system and its performance, cost, security metrics, and operational characteristics.
ULO4: Design, build, test and verify, a trustworthy, hardware system that meets its specifications with regard to both functionality and security.

General Assessment Information

Grading and passing requirement for unit

In order to pass this unit a student must obtain a mark of 50 or more for the unit (i.e. obtain a passing grade P/CR/D/HD).

For further details about grading, please refer below in the policies and procedures section.

Hurdle Requirements

There are no hurdle requirements.

Late Assessment Submission Penalty

From 1 July 2022, Students enrolled in Session based units with written assessments will have the following university standard late penalty applied. Please see https://students.mq.edu.au/study/assessment-exams/assessments for more information.

Unless a Special Consideration request has been submitted and approved, a 5% penalty (of the total possible mark) will be applied each day a written assessment is not submitted, up until the 7^th day (including weekends). After the 7^th day, a grade of '0' will be awarded even if the assessment is submitted. Submission time for all written assessments is set at 11:55 pm. A 1-hour grace period is provided to students who experience a technical concern.

For any late submission of time-sensitive tasks, such as scheduled tests/exams, performance assessments/presentations, and/or scheduled practical assessments/labs, students need to submit an application for Special Consideration.

Assessments where Late Submissions will be accepted

In this unit, late submissions will accepted as follows:

Assignment 1 report, Assignment 2 report and Project Report – YES, Standard Late Penalty applies

Assessment Tasks

Name	Weighting	Hurdle	Due
Assignment 1	10%	No	Week 4
Assignment 1 Defence	15%	No	Week 4
Assignment 2	10%	No	Week 7
Assignment 2 Defence	15%	No	Week 7
Project Report	20%	No	Week 13
Project Defence	30%	No	Exam Period