Students

ELEC2042 – Digital Circuits and Systems

2025 – Session 2, In person-scheduled-weekday, North Ryde

General Information

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Unit convenor and teaching staff Unit convenor and teaching staff Unit Convenor
Hazer Inaltekin
hazer.inaltekin@mq.edu.au
Contact via 9850 2280
44 WTR, Room 133
Appointment via email
Tutor
Meer Shadman Saeed
meershadman.saeed@mq.edu.au
Contact via Contact via email
44 WTR
Appointment via email
Credit points Credit points
10
Prerequisites Prerequisites
COMP1000
Corequisites Corequisites
Co-badged status Co-badged status
Unit description Unit description

This unit aims to provide students with an understanding of, and fluency in, combinational and sequential logic design techniques commonly used in the design of large-scale digital systems, as well as exposure to hardware description languages. Students will apply this knowledge to the design and implementation of digital circuits and systems at the gate level, and also program field programmable gate arrays. 

Learning in this unit enhances student understanding of global challenges identified by the United Nations Sustainable Development Goals (UNSDGs) Industry, Innovation and Infrastructure

Important Academic Dates

Information about important academic dates including deadlines for withdrawing from units are available at https://www.mq.edu.au/study/calendar-of-dates

Learning Outcomes

On successful completion of this unit, you will be able to:

  • ULO1: Demonstrate an understanding of different number systems used in digital systems and be able to convert between them. 
  • ULO2: Design fast and efficient logic circuits by applying standard minimisation techniques.
  • ULO3: Relate state-diagrams, truth tables, wave forms and logic equations as different representations of the same synchronous sequential machine.
  • ULO4: Describe and document digital logic circuits and systems using industry-standard languages and tools
  • ULO5: Implement digital logic circuits and systems in hardware

General Assessment Information

Grading and passing requirement for unit

The assessment tasks are a final exam, a unit project, and a workshop report. The unit project will be assessed based on a written report and a software-based circuit model.

In order to pass this unit a student must obtain a mark of 50 or more for the unit (i.e. obtain a passing grade P/ CR/ D/ HD). 

For further details about grading, please refer below in the policies and procedures section.

Late submissions and Resubmissions

Resubmission of work is not allowed. 

Unless a Special Consideration request has been submitted and approved, a 5% penalty (of the total possible mark of the task) will be applied for each day a written report or presentation assessment is not submitted, up until the 7th day (including weekends). After the 7th day, a grade of ‘0’ will be awarded even if the assessment is submitted. The submission time for all uploaded assessments is 11:59pm. A 1-hour grace period will be provided to students who experience a technical concern. 

For any late submission of time-sensitive tasks, such as scheduled reports and simulation files, please apply for Special Consideration. 

Detailed list of assessments where late submissions WILL be accepted but standard late penalties will apply: Unit Design Implementation Project and Digital Design Workshop Report. 

Detailed list of assessments where late submissions WILL NOT be accepted unless Special Consideration is granted: Final Exam. 

Special Consideration

The Special Consideration Policy aims to support students who have been impacted by short-term circumstances or events that are serious, unavoidable and significantly disruptive, and which may affect their performance in assessment. If you experience circumstances or events that affect your ability to complete the assessments in this unit on time, please inform the convenor and submit a Special Consideration request through ask.mq.edu.au. 

Assessment Tasks

Name Weighting Hurdle Due
Final Exam 40% No Scheduled S2 Exam Period
Design Implementation Project 30% No Week 8
Digital Design Workshop Report 30% No Week 12

Final Exam

Assessment Type 1: Examination
Indicative Time on Task 2: 20 hours
Due: Scheduled S2 Exam Period
Weighting: 40%

 

The final examination for this unit will be conducted face-to-face under supervised (invigilated) conditions. It will assess all topics covered throughout the session and test students' understanding and application of key concepts.

 
On successful completion you will be able to:
  • Demonstrate an understanding of different number systems used in digital systems and be able to convert between them. 
  • Design fast and efficient logic circuits by applying standard minimisation techniques.
  • Relate state-diagrams, truth tables, wave forms and logic equations as different representations of the same synchronous sequential machine.
  • Describe and document digital logic circuits and systems using industry-standard languages and tools

Design Implementation Project

Assessment Type 1: Design Task
Indicative Time on Task 2: 30 hours
Due: Week 8
Weighting: 30%

 

This is the mid-semester design assignment. You will take the knowledge about digital circuits presented so far and design a circuit to perform a given task.

 
On successful completion you will be able to:
  • Demonstrate an understanding of different number systems used in digital systems and be able to convert between them. 
  • Design fast and efficient logic circuits by applying standard minimisation techniques.

Digital Design Workshop Report

Assessment Type 1: Practice-based task
Indicative Time on Task 2: 12 hours
Due: Week 12
Weighting: 30%

 

Students will complete a series of design-focused practical tasks throughout the session. To support their learning, preparatory materials will be provided ahead of each practical session. Students will submit a workshop report for assessment at the end of the session.

 
On successful completion you will be able to:
  • Demonstrate an understanding of different number systems used in digital systems and be able to convert between them. 
  • Design fast and efficient logic circuits by applying standard minimisation techniques.
  • Relate state-diagrams, truth tables, wave forms and logic equations as different representations of the same synchronous sequential machine.
  • Describe and document digital logic circuits and systems using industry-standard languages and tools
  • Implement digital logic circuits and systems in hardware

1 If you need help with your assignment, please contact:

  • the academic teaching staff in your unit for guidance in understanding or completing this type of assessment
  • the Writing Centre for academic skills support.

2 Indicative time-on-task is an estimate of the time required for completion of the assessment task and is subject to individual variation

Delivery and Resources

Each week students are expected to attend a 2-hour lecture and a 3-hour practical session on campus. The students will be provided with lecture slides each week in iLearn. Practical sheets and projects will also be posted to iLearn. There may be pre-work that needs to be completed before each practical session, which may include watching videos and completing exercises. 

This is a hands-on unit, centred around digital logic circuits. We will be using physical trainer boards to build digital circuits and experiment with those circuits, along with building full digital systems using simulation software tools. All students are expected to attend their practical session on campus to access the hardware.

The following textbooks will be used: 

  • Digital Design and Computer Architecture (MIPS Version), 2nd Edition by D. M. Harris and S. L. Harris 
  • Digital Design with an Introduction to the Verilog HDL, VHDL and System Verilog, 6th Edition by M. M. R. Mano and M. D. Ciletti

 Both books are available free of charge to students through the library. 

Policies and Procedures

Macquarie University policies and procedures are accessible from Policy Central (https://policies.mq.edu.au). Students should be aware of the following policies in particular with regard to Learning and Teaching:

Students seeking more policy resources can visit Student Policies (https://students.mq.edu.au/support/study/policies). It is your one-stop-shop for the key policies you need to know about throughout your undergraduate student journey.

To find other policies relating to Teaching and Learning, visit Policy Central (https://policies.mq.edu.au) and use the search tool.

Student Code of Conduct

Macquarie University students have a responsibility to be familiar with the Student Code of Conduct: https://students.mq.edu.au/admin/other-resources/student-conduct

Results

Results published on platform other than eStudent, (eg. iLearn, Coursera etc.) or released directly by your Unit Convenor, are not confirmed as they are subject to final approval by the University. Once approved, final results will be sent to your student email address and will be made available in eStudent. For more information visit connect.mq.edu.au or if you are a Global MBA student contact globalmba.support@mq.edu.au

Academic Integrity

At Macquarie, we believe academic integrity – honesty, respect, trust, responsibility, fairness and courage – is at the core of learning, teaching and research. We recognise that meeting the expectations required to complete your assessments can be challenging. So, we offer you a range of resources and services to help you reach your potential, including free online writing and maths support, academic skills development and wellbeing consultations.

Student Support

Macquarie University provides a range of support services for students. For details, visit http://students.mq.edu.au/support/

Academic Success

Academic Success provides resources to develop your English language proficiency, academic writing, and communication skills.

The Library provides online and face to face support to help you find and use relevant information resources. 

Student Services and Support

Macquarie University offers a range of Student Support Services including:

Student Enquiries

Got a question? Ask us via the Service Connect Portal, or contact Service Connect.

IT Help

For help with University computer systems and technology, visit http://www.mq.edu.au/about_us/offices_and_units/information_technology/help/. 

When using the University's IT, you must adhere to the Acceptable Use of IT Resources Policy. The policy applies to all who connect to the MQ network including students.

Engineers Australia Competency Mapping

EA Competency Standard

Unit Learning Outcomes

Knowledge and Skill Base

1.1 Comprehensive, theory-based understanding of the underpinning fundamentals applicable to the engineering discipline.

ULO2

1.2 Conceptual understanding of underpinning maths, analysis, statistics, computing.

ULO1, ULO3

1.3 In-depth understanding of specialist bodies of knowledge

ULO1, ULO4, ULO5

1.4 Discernment of knowledge development and research directions

 

1.5 Knowledge of engineering design practice

ULO2, ULO5

1.6 Understanding of scope, principles, norms, accountabilities of sustainable engineering practice.

 

Engineering Application Ability

2.1 Application of established engineering methods to complex problem solving

ULO1, ULO3, ULO4, ULO5

2.2 Fluent application of engineering techniques, tools and resources.

ULO1, ULO2

2.3 Application of systematic engineering synthesis and design processes.

ULO4

2.4 Application of systematic approaches to the conduct and management of engineering projects.

 

Professional and Personal Attributes

3.1 Ethical conduct and professional accountability.

 

3.2 Effective oral and written communication in professional and lay domains.

 

3.3 Creative, innovative and pro-active demeanour.

 

3.4 Professional use and management of information.

 

3.5 Orderly management of self, and professional conduct.

 

3.6 Effective team membership and team leadership

 

Unit information based on version 2025.04 of the Handbook