Grading and passing requirement for unit

In order to pass this unit, a student must obtain a mark of 50 or more for the unit (i.e. obtain a passing grade P/ CR/ D/ HD). For further details about grading, please refer below in the policies and procedures section.

Late submissions and Resubmissions

Resubmission of work is not allowed.

Unless a Special Consideration request has been submitted and approved, a 5% penalty (of the total possible mark of the task) will be applied for each day an assessment is not submitted, up until the 7th day (including weekends). After the 7th day, a grade of ‘0’ will be awarded even if the assessment is submitted. The submission time for all uploaded assessments is 11:55 pm. A 1-hour grace period will be provided to students who experience a technical concern.

For any late submission of time-sensitive tasks, such as scheduled tests/exams, performance assessments/presentations, and/or scheduled practical assessments/labs, students need to submit an application for Special Consideration.

Assessments where Late Submissions will be accepted

In this unit, late submissions will accepted as follows: 

Assignment, Project – YES, Standard Late Penalty applies;

Test – NO, unless Special Consideration is Granted.

This unit consists of lectures and practical sessions on campus. Students are expected to attend both, and complete the necessary preparation prior to attending the classes.

You will be using the Xilinx Vivado HL Design Edition to program a Zynq Ultrascale+ MPSoC (on an Ultra96 development board) for your practicals and assessments. The Vivado design tools will be available on the computers in the lab but you should also install it onto your own laptop so that you can work on the assignment and project at home. You will need access to a Windows laptop with at least 8 GB RAM and ~41 GB of free hard drive space.

Access to the Ultra96 development board will be made available during the 4-hour weekly practical sessions. Hence, it is important to attend all practicals to ensure you have sufficient time to complete the practicals and assessments. While some practical weeks are dedicated to working on the project, students must also spend sufficient time outside of class in order to complete the project.

This unit covers high level synthesis, hardware/software partitioning, Zynq Ultrascale+ MPSoC Architecture, and PYNQ. The unit uses both C and Python languages. Hence, students are expected to be able to write a computer program prior to attempting this unit. They should also have a basic understanding of computer architecture. There is no textbook for this unit. Additional reading and learning resources will be provided through the unit's iLearn page.

Refer to iLearn for details.

Structure of the assessments have been revised to comply with the University's policy.