| Unit convenor and teaching staff |
Unit convenor and teaching staff
Unit Convener and Lecturer in Charge
Ediz Cetin
Contact via Email
9 Wally's Walk
Monday’s 14:00 – 16:00 hrs.
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| Credit points |
Credit points
10
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| Prerequisites |
Prerequisites
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| Corequisites |
Corequisites
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| Co-badged status |
Co-badged status
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| Unit description |
Unit description
This unit will provide an in-depth introduction to the principal concepts, foundations, and methodologies for the design of trustworthy security systems on hardware. Specifically, the unit aims to equip students with the skills needed to build secure and trustworthy hardware using Field Programmable Gate Array (FPGA) technology. The unit will cover topics in cryptosystems, error coding techniques as well as state-of-the-art hardware security systems. The unit will also provide the students with an understanding of and fluency in the quantitative evaluation of design alternatives while considering design metrics such as performance, power dissipation, cost and security. Learning in this unit enhances student understanding of global challenges identified by the United Nations Sustainable Development Goals (UNSDGs) Industry, Innovation and Infrastructure |
Information about important academic dates including deadlines for withdrawing from units are available at https://www.mq.edu.au/study/calendar-of-dates
On successful completion of this unit, you will be able to:
Grading and passing requirement for unit
In order to pass this unit a student must obtain a mark of 50 or more for the unit (i.e. obtain a passing grade P/CR/D/HD).
For further details about grading, please refer below in the policies and procedures section.
Hurdle Requirements
There are no hurdle requirements.
Late Assessment Submission Penalty
5% penalty per day: If you submit your assessment late, 5% of the total possible marks will be deducted for each day (including weekends), up to 7 days.
Example 1 (out of 100): If you score 85/100 but submit 20 hours late, you will lose 5 marks and receive 80/100.
Example 2 (out of 30): If you score 27/30 but submit 1 day late, you will lose 1.5 marks and receive 25.5/30.
After 7 days: Submissions more than 7 days late will receive a mark of 0.
Extensions:
Automatic short extension: Some assessments are eligible for automatic short extension. You can only apply for an automatic short extension before the due date.
Special Consideration: If you need more time due to serious issues and for any assessments that are not eligible for Short Extension, you must apply for Special Consideration.
Need help? Review the Special Consideration page HERE
| Name | Weighting | Hurdle | Due | Groupwork/Individual | Short Extension | AI assisted? |
|---|---|---|---|---|---|---|
| Assignment 1 | 20% | No | 15/03/2026 | Individual | No | |
| Assignment 2 | 30% | No | 03/05/2026 | Individual | No | |
| Project Defence | 50% | No | Exam Period | Individual | No |
Assessment Type 1: Written Submission
Indicative Time on Task 2: 26 hours
Due: 15/03/2026
Weighting: 20%
Groupwork/Individual: Individual
Short extension 3: No
AI assisted?:
You will design a device-to-device communication system using hardware description languages and prepare a report detailing your proposed solution. Design review reports are commonly used in industry to communicate and justify engineering decisions. Your report will include the system architecture, verification results, and technical discussion. This task helps you build skills in secure system design, simulation, verification and professional documentation.
Assessment Type 1: Written Submission
Indicative Time on Task 2: 30 hours
Due: 03/05/2026
Weighting: 30%
Groupwork/Individual: Individual
Short extension 3: No
AI assisted?:
You will implement a secure processing module based on a cryptographic algorithm and integrate it with your device-to-device communication system. You will prepare a design review report presenting your design solution, supported by simulation results, verification evidence, and discussion of design trade-offs. This task helps you develop skills in secure hardware design, integration, and evaluation using FPGA tools.
Assessment Type 1: Presentation task
Indicative Time on Task 2: 55 hours
Due: Exam Period
Weighting: 50%
Groupwork/Individual: Individual
Short extension 3: No
AI assisted?:
You will present and defend your complete secure hardware system, including its design rationale, implementation outcomes, and evaluation results. This task supports your ability to articulate complex technical concepts, reflect on design decisions, and demonstrate mastery of secure system development.
1 If you need help with your assignment, please contact:
2 Indicative time-on-task is an estimate of the time required for completion of the assessment task and is subject to individual variation.
3 An automatic short extension is available for some assessments. Apply through the Service Connect Portal.
Textbook: None required to purchase. Lecturer will provide the reading material.
Methods of Communication: We will communicate with you via your university email and through announcements on iLearn. Queries to convenors can either be placed on the iLearn discussion board or sent to the unit convenor via the contact email on iLearn
Macquarie University policies and procedures are accessible from Policy Central (https://policies.mq.edu.au). Students should be aware of the following policies in particular with regard to Learning and Teaching:
Students seeking more policy resources can visit Student Policies (https://students.mq.edu.au/support/study/policies). It is your one-stop-shop for the key policies you need to know about throughout your undergraduate student journey.
To find other policies relating to Teaching and Learning, visit Policy Central (https://policies.mq.edu.au) and use the search tool.
Macquarie University students have a responsibility to be familiar with the Student Code of Conduct: https://students.mq.edu.au/admin/other-resources/student-conduct
Results published on platform other than eStudent, (eg. iLearn, Coursera etc.) or released directly by your Unit Convenor, are not confirmed as they are subject to final approval by the University. Once approved, final results will be sent to your student email address and will be made available in eStudent. For more information visit connect.mq.edu.au or if you are a Global MBA student contact globalmba.support@mq.edu.au
At Macquarie, we believe academic integrity – honesty, respect, trust, responsibility, fairness and courage – is at the core of learning, teaching and research. We recognise that meeting the expectations required to complete your assessments can be challenging. So, we offer you a range of resources and services to help you reach your potential, including free online writing and maths support, academic skills development and wellbeing consultations.
Macquarie University provides a range of support services for students. For details, visit http://students.mq.edu.au/support/
Academic Success provides resources to develop your English language proficiency, academic writing, and communication skills.
The Library provides online and face to face support to help you find and use relevant information resources.
Macquarie University offers a range of Student Support Services including:
Got a question? Ask us via the Service Connect Portal, or contact Service Connect.
For help with University computer systems and technology, visit http://www.mq.edu.au/about_us/offices_and_units/information_technology/help/.
When using the University's IT, you must adhere to the Acceptable Use of IT Resources Policy. The policy applies to all who connect to the MQ network including students.
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EA Competency Standard |
Unit Learning Outcomes |
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Knowledge and Skill Base |
1.1 Comprehensive, theory-based understanding of the underpinning fundamentals applicable to the engineering discipline. |
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1.2 Conceptual understanding of underpinning maths, analysis, statistics, computing. |
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1.3 In-depth understanding of specialist bodies of knowledge |
1, 2 |
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1.4 Discernment of knowledge development and research directions |
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1.5 Knowledge of engineering design practice |
1, 2 |
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1.6 Understanding of scope, principles, norms, accountabilities of sustainable engineering practice. |
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Engineering Application Ability |
2.1 Application of established engineering methods to complex problem solving |
3, 4 |
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2.2 Fluent application of engineering techniques, tools and resources. |
3, 4 |
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2.3 Application of systematic engineering synthesis and design processes. |
4 |
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2.4 Application of systematic approaches to the conduct and management of engineering projects. |
3, 4 |
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Professional and Personal Attributes |
3.1 Ethical conduct and professional accountability. |
1 ,2 |
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3.2 Effective oral and written communication in professional and lay domains. |
3, 4 |
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3.3 Creative, innovative and pro-active demeanour. |
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3.4 Professional use and management of information. |
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3.5 Orderly management of self, and professional conduct. |
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3.6 Effective team membership and team leadership |
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Unit information based on version 2026.02 of the Handbook